Analog Design Bench
Measuring frontier coding agents on original, long-horizon analog circuit design tasks
Analog circuit design has always been the domain where intuition meets physics. We built Analog Design Bench to measure whether AI agents can navigate real design trade-offs: PVT corners, Monte Carlo yield, startup transients, noise budgets. Fifty tasks, twenty-one models, thousands of SPICE simulations.
Design a Sky130 high-impedance first-order bandgap core
Build a startup-safe CTAT/PTAT bias/reference core meeting voltage, tempco, line-regulation, supply-coupling, power, noise, and Monte Carlo limits across PVT.
Design a 1 GHz Sky130 Divide-by-Two Flip-Flop
Using the SKY130 130 nm CMOS process, design a transistor-level divide-by-two flip-flop operating at 1 GHz.
Design a Sky130 2.4 GHz Inductive-Degeneration LNA
Design a transistor-level 2.4 GHz inductively degenerated LNA with 12 dB gain and 2 dB noise figure.
Design a Sky130 3-bit Flash ADC
A clocked 3-bit flash ADC graded on linearity, dynamic coding, delay, overdrive, and power across PVT.
Design a 3.3-to-3.8 GHz broadband 50-to-200 ohm match
Synthesize a finite-Q lumped passive network that matches a 200 ohm RF load to a 50 ohm source.
Design a Sky130 capacitively coupled neural amplifier
Build a micro-power capacitively coupled neural amplifier meeting gain, band-corner, stability, noise, and distortion targets.
A passing run from claude-fable-5 on the bandgap reference task. The agent wrote this SPICE netlist after 42 steps and 44 minutes, passing all 12 verification checks.
* First-order SKY130 bandgap reference core
* Topology: PTAT core with Q1 (1x) vs Q2 (24x) + R1
* Output: mirrored PTAT current into R2 + Q3 gives vref ~ 1.22V
.subckt bandgap_reference vss vdd vref
* PTAT core BJTs
XQ1 na na vss vss sky130_fd_pr__npn_05v5_W1p00L1p00 mult=1
XQ2 nq2 nq2 vss vss sky130_fd_pr__npn_05v5_W1p00L1p00 mult=24
R1 nb nq2 17k
* Output branch
XQ3 nc nc vss vss sky130_fd_pr__npn_05v5_W1p00L1p00 mult=1
R2 vref nc 92k
CO vref vss 10p
* PMOS mirror
XMP1 na pgate vdd vdd sky130_fd_pr__pfet_01v8_lvt l=8 w=32 nf=4
XMP2 nb pgate vdd vdd sky130_fd_pr__pfet_01v8_lvt l=8 w=32 nf=4
XMP3 vref g3 vdd vdd sky130_fd_pr__pfet_01v8_lvt l=8 w=32 nf=4
* Error amplifier (5T OTA)
XM1 x1 nb ntail vss sky130_fd_pr__nfet_01v8_lvt l=1 w=16 nf=4
XM2 pgate na ntail vss sky130_fd_pr__nfet_01v8_lvt l=1 w=16 nf=4
XML1 x1 x1 vdd vdd sky130_fd_pr__pfet_01v8_lvt l=8 w=32 nf=4
XML2 pgate x1 vdd vdd sky130_fd_pr__pfet_01v8_lvt l=8 w=32 nf=4
.ends bandgap_reference| # | Model | Pass@1 | Cost | Output | Time |
|---|---|---|---|---|---|
| 1 | claude-fable-5[max] | 79% | $21.88 | 113k | 58m |
| 2 | gpt-5-6-sol[max] | 67% | $13.91 | 75k | 52m |
| 3 | claude-opus-5-max[max] | 66% | $26.37 | 177k | 1h 41m |
| 4 | claude-opus-4-8[max] | 63% | $18.52 | 199k | 1h 18m |
| 5 | gpt-5-6-sol[xhigh] | 57% | $7.00 | 48k | 36m |
| 6 | kimi-k3-1m | 54% | $3.81 | 103k | 1h 34m |
| 7 | gpt-5-6-terra[max] | 48% | $8.15 | 101k | 1h 04m |
| 8 | qwen-3-8-max | 45% | $4.00 | 206k | 1h 51m |
| 9 | deepseek-v4-flash-0731 | 43% | $0.18 | 384k | 1h 21m |
| 10 | glm-5-2 | 42% | $16.48 | 174k | 1h 41m |
| 11 | doubao-seed-evolving | 41% | $1.50 | 121k | 1h 37m |
| 12 | gpt-5-6-luna[max] | 41% | $1.03 | 120k | 1h 12m |
Each agent receives a natural-language spec, a starter netlist, and access to ngspice. It must iterate on the circuit until all verification checks pass. No hints, no partial credit. The evaluator runs the same SPICE testbenches used to sign off real silicon.