Multiagent RL for chip design.
We train teams of agents on long-horizon RTL-to-GDS tasks. The main agent is the VP, orchestrating subagents and delivering the final handoff. Each specialist subagent gets its own tools, its own context, its own reward.
One agent. One long rollout.
Tries to do everything (architecture, RTL, DV, PD) in a single conversation.
User
design spec
Single Agent
one LLM
Long context rollout
> think about architecture...
> generate microarchitecture...
> write RTL...
> run simulation...
> debug errors...
> create testbench...
> write assertions...
> run formal...
> fix bugs...
> synthesize...
> place and route...
> analyze timing...
... (repeats)
~0K tokens
Specialists. In parallel.
Architect, RTL, DV, and PD agents collaborate through shared context and tools.
Test-Time Compute Optimization
Chip design is simulation-heavy: every tool run dumps thousands of lines of logs, waveforms, and timing reports. Multiagent is how we allocate test-time compute per role — each specialist's full context window is spent on its own tool feedback instead of being diluted across the whole flow.
Reward shaping
A single agent gets one sparse reward at tapeout. Separate agents get dense, role-appropriate rewards: MicroArch is rewarded on performance against the golden model, DV on coverage and bugs found, PD on timing closure and DRC, RTL on passing checks.
A VP of DV main agent orchestrates subagents that each own one verification leg: formal, UVM testbenches, simulation, emulation. The VP reads the verification plan, assigns coverage targets, and triages failures back to the right subagent.
A single agent gets context polluted across methods, no clean per-method reward, and failures triaged by the same polluted context that caused them.
VP of DV
main agent
↓ tasks + coverage targets · ↑ rewards
Formal
proofs, cex
UVM
coverage, bugs
Simulation
pass rate
Emulation
bugs, cycles
session 1 · main agent
session 2 · subagent (role X)
session server · one model
TITO · clean per-role trajectories → data buffer
trainer · one update, mixed batches
knob: batch composition + per-role advantage scale
before — step 0 · GLM-4.6-Air base
> one 800-line testbench covering everything
> mixes formal + sim in one file
> no coverage targets assigned
after — step 70
> dispatches Formal on assert_*
> UVM coverage targets: 32 bins, 95% goal
> triages cex → Simulation subagent
GRPO on top of GLM-4.6-Air, illustrative
Production RL experience from xAI, OpenAI, and Ricursive, with engineers from NVIDIA and Fireworks.
Our team has trained frontier models, built large-scale inference stacks, and taped out real silicon. We're passionate about using model intelligence to build the best infrastructure.
Chirp
Our meta-harness for chip design — agents that iterate on the harness itself. Read the write-up.
Read →Generated Digital Modules
100+ verified RTL-to-GDS blocks across interfaces, cryptography, DSP, and compute
Read →Analog Design Bench
Measuring frontier agents on long-horizon analog circuit design tasks
Read →