Physical Intuition / Blog
Generated Digital Modules
100+ verified RTL-to-GDS blocks, fully autonomous
These are not hand-drawn layouts. Every block shown was generated by Chirp from a natural-language spec, synthesized through open-source EDA, and verified for timing, DRC, and functional correctness. Each thumbnail is a real layout from a real run.
Interfaces, Interconnects & Communication
AXI4WishboneSPIUARTI²CUSBNoC1-WireQSPI
Cryptography, Channel Coding & Data Integrity
AESAES-GCMSHA-256MD5XTEAPRESENTCRCReed-SolomonViterbiHamming
DSP, Machine Learning & Multimedia
FFTFIRFlashAttentionSoftmaxTiny-NPUMatrix ArraysImage FiltersMDCT
Processors, Floating-Point & Compute
FP32 FPUFP64 FPUSAP-1SIMT GPUOR1200 Cache/MMUPower Management
Timing, Control, Storage & Low-Power
TimersFrequency CounterEvent CounterSingle-Port RAMBanked SRAMClock-Gated Registers
Every generated module passes through the same rigorous flow before it ships:
01
Open-Source EDA
OpenROAD Flow Scripts with ASAP7 and SKY130
02
RTL → GDS
Full synthesis, placement, routing to manufacturable layout
03
STA Timing Closure
Static timing analysis with zero setup/hold violations
04
DRC = 0
Zero design rule violations on final layout
05
Post-Sim Verification
Gate-level simulation with coverage and power analysis